The present invention relates to CMOS integrated circuits, i.e., to integrated circuits containing both N-channel and P-channel insulated gate field effect devices.
It is widely recognized in the art that it would be highly desirable to achieve practical stacked CMOS integrated circuits, i.e., circuits where a single gate at a single location is capacitively coupled to control both N-channel and P-channel devices. It is usually assumed that the N-channel devices would be formed in the substrate and the P-channel devices would be formed in polysilicon, although this is not strictly necessary.
Stacked CMOS has the potential to provide extremely dense integrated circuits, and especially to provide extremely dense memory circuits. However, known methods for fabrication of stacked CMOS structures do not permit the overlayed device to be self-aligned. That is, the mask which is used to pattern the channel region of the overlayed polysilicon is applied in a separate masking step from the patterning of the gate which must address this channel. This means that small geometry devices become infeasible, since misalignment between the gate and channel region would introduce a disastrous spread in device characteristics. The source-to-gate and drain-to-gate overlap capacitances are increased if the overlayed device is not self-aligned.
A stacked CMOS structure is described by S. Malhi in U.S. application No. 505,155, filed June 17, 1983, and assigned to the assignee of the present application, now issued as U.S. Pat. No. 4,502,202, entitled "Method for Fabricating Overlaid Device in Stacked CMOS". The method described therein is not fully self-aligned, resulting in higher overlap capacitances.
Thus it is an object of the present invention to provide a method for fabricating stacked CMOS integrated circuits wherein an overlayed polysilicon device has a channel region which is fully self-aligned to a gate electrode beneath the channel region.
Thus, according to the present invention, a gate oxide is formed over the gate region, followed by a layer of polycrystalline silicon. A doped layer is formed over the polycrystalline silicon layer, and etched back to expose the polycrystalline silicon over the gate region. Annealing the integrated circuit in an inert ambiant causes dopant to diffuse from the doped layer into the polycrystalline silicon, thereby forming heavily doped source and drain regions within the polycrystalline silicon, and separated by a less heavily doped channel region directly above the gate region.
The novel features which characterize the present invention are defined by the appended claims. The foregoing and other objects and advantages of the present invention will hereinafter appear, and for purposes of illustration, but not of limitation, a preferred embodiment is described in the accompanying drawings.